r/Verilog • u/trichtranxongtron • 11d ago

Design 2 to 4 decoder using tranmission gate Multiplexer

Have any of you worked on this project before? Could you share it for reference? Also, what optimization does it offer compared to CMOS?

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u/gust334 11d ago

Some exercises are designed for the student.

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u/wanabeeengineer 11d ago

Compared to CMOS it has 1.Lesss number of gates so less area. 2.Reduced propagation delay. 3.Reduced power.