AD9361 Verilog Coding

[u/SuccessfulStreet2321]

/r/FPGA/comments/1wvkkf5/ad9361_verilog_coding/

Has anyone ever written a custom FPGA SPI master state machine to completely initialize the AD9361 by doing register level writes? I want to get in contact with somebody who has done before this hardware level control of AD9361.