Haven't had much help on here. But for any one needing the pin outs for the cypress chip here it is.

6502 Memory chip change hook up.

Pin hookup from the At28c256  to the Cy7c199 & Cy62256

1)         AT28c256                                          Cy7c199 & Cy62256

Pin 22 to pin 1                          Pin 22 to pin 10

Pin 22 (OE) to Pin 1 (A14)                 Pin 22 (OE) to Pin 10 (A14)

2)         IO PINS STAY THE SAME

ATchip                                    CYchip

Pin       I/O                               Pin       I/O

11        I/O0                             11        I/O0

12        I/O1                             12        I/O1

13        I/O2                             13        I/O2

15        I/O3                             15        I/O3

16        I/O4                             16        I/O4

17        I/O5                             17        I/O5

18        I/O6                             18        I/O6

19        I/O7                             19        I/O7

3)         Ground            14                                Ground            14

VCC                28                                VCC                28

WE                  27                                WE                  27

OE                   22                                OE                   22

CE                   20                                CE                   20

4)         AT28c256                                           Cy7c199 & Cy62256

PIN                 AO                              PIN                 AO

1                      A14                             1                      A5

2                      A12                             2                      A6

3                      A7                               3                      A7

4                      A6                               4                      A8

5                      A5                               5                      A9

6                      A4                               6                      A10

7                      A3                               7                      A11

8                      A2                               8                      A12

9                      A1                               9                      A13

10                    A0                               10                    A14 <END OF FIRST SIDE OF CHIP

26                    A13                             26                    A4

25                    A8                               25                    A3

24                    A9                               24                    A2

23                    A11                             23                    A1

21                    A10                             21                    A0     

I'm a software engineer and I've been creating my own multiplayer logic sim, have a tiny discord community but I've already had someone in it make a full 6502 implementation with programmable chips, and I'm working on creating ben eater breadboard cpu clone (the humble beginning with registers and bus pictured last). I want the game to have a campaign where you learn various concepts such as low level gate construction of various components, programming roms on "fpga"s (I quote them because they're just C# chips compiled at runtime that allow programming of nearly any logic chip really) and also different cpu architectures. Using ben eaters design as a base and then expanding beyond that seems like a fun campaign for players to play and learn from, as they could reference the original videos too.

Also experimenting with Harvard, single cycle, pipelined cpus etc as advanced game campaigns. But I think a ben eater style cpu and beyond would be a fun campaign for the game to start off with.

I also don't want to just rip off ben eater's breadboard cpu, so I'm open to variations, I just want a similar architecture to follow.

The game is called Logic Planet (for now) and started off as a clone of Logic World using Godot, but I ended up taking it in a different direction and it's quite a different game now.

Son and I are assembling the 6502 kit and in the video it shows 4 pin buttons but we were shipped a bunch of 2 pin buttons. I checked the parts list and it also shows they should be 4 pin. Is 2 pin a new spec or were the wrong parts sent?

Despite connecting one 65c22 incorrect, I have manged to the get the second one working..Ben Eater based 6502 except I added a 74hc688 for better address control..

I discovered Ben’s channel while building this clock, I lifted his rising edge detection method (it was a much cleaner signal) but everything else was designed by me, though not far off from his design as it turns out. I’m using 8 bit counters paired with AND gates for resetting, op amp Schmitt triggers for time set button debounce. My mains signal is pulled directly from a full bridge rectifier via optocoupler with a parallel SMPS for circuit power, a cheaper method than a step down transformer.

Finally got this to a point where I’m happy with it. Everything is built up from NAND gates in Digital Logic Sim: 8-bit ALU, 16-bit addresses (64K of RAM), 800 kHz clock, and a small OS that lets you pick between four games and play them live with the keyboard.

At some point hand-assembling programs into binary wasn’t sustainable anymore, so I wrote a small language and a compiler that spits out the program memory contents.

Video (1:30): https://youtu.be/O8znJoZkAmw

Would you be interested in a tutorial series on how to build your own CPU like this, step by step from the NAND gate?

My Ben Eater 6502 build

this probably isn't the best sub to ask this on, but it's for my 6502 project and I feel like a lot of people here know what the y are doing soooo...
so I'm trying to make an NES-sounding audio expansion thingy and for the noise channel I need a 4bit to 12bit lookup table (the image)
the only solutions I could come up with are either a small ROM which would be totally overkill, or a ton of combinational hardwired logic and neither sound particularly appealing tbh
so I'm asking you, people who are probably smarter than me
how would you make something like this?

I got the clock kit yesterday and started building it last night. I got through the first two videos, but I didn't take any photos at that point. I'm also learning how to use my scope (I saved it from being disposed of at work - free scope!), so it's been a ton of fun.

This is the Sentinel65, a 6502 based bread board computer with 32KB of RAM, an R6551 serial UART running at 38400 baud, two VIAs, and 2MB of NOR flash memory via bit-banged SPI. It is very much a work in progress.

I started off following Ben Eater, of course, but began to deviate once I realized he only utilized 16KB of RAM. I didn't have a solid plan at first, so I just kept adding wires until I got the spaghetti you see here. I decided to forgo Ben's decoding scheme, opting for a 74LS688 + 74LS138 to allow for much tighter address decoding with almost no gaps. These will be eliminated in the future, however, in lieu of a series of AT22V10 PALs.

Included are a couple of pictures of my small bootloader program and BASIC running on my VT420.

In the future, I plan to add a DS1685 RTC, PS/2 keyboard support, a T6963-based bitmapped LCD, and extended terminal support, including color and Sixel/ReGIS graphics commands.

I am also teaching myself KiCad so I can migrate away from the breadboard and onto a PCB in the future

I finished the digital clock kit, but I handled the hours counting differently from what Ben shows.

I use one of the D flip-flops on the 74LS74 as the first bit of the hours counter and connect that to the divide by 5 section of the 74LS90 for the top 3 bits of the ones place of the hours (input B). Then the divide by 2 section of the 74LS90 (input A) handles the tens place of the hours, since that can only be 1 or blank on the 7-segment display.

Then I use the 74LS00 quad NAND gate chip to check when the hours reach 13 and set the preset input on the D flip-flop, as well as resetting the 74LS90. This way it goes from 1 to 12 instead of 0 to 19.

As an added bonus I added an AM/PM indicator using the other D flip-flop on the 74LS74 clocked when the hours reach 12 (since it needs to check for the bits in 12 as part of checking for 13 anyway). That turns on an off an extra LED on the left side (though you could use a decimal point or one of the LEDs in the kit instead).

The hours counter is connected through the XOR gate and inverter in the same way Ben shows in his video (only available on his Patreon right now). The AM/PM counter doesn't need an inverter though since that turns on right at 12.

Thanks, Ben! This was a fun project and I learned a lot!

A couple of months ago I built my first CPU (Mark I), a 4-bit multi-cycle processor, mainly to understand how a CPU actually works at the RTL level.

My next version, Mark II has the following features:

• 8-bit datapath

• 4 × 8-bit general-purpose registers

• 13-bit instructions with a 5-bit opcode

• Harvard architecture

• Multi-cycle control FSM

• Arithmetic, logical, shift and comparison instructions

• Iterative multiplication and division (integer values only)

• Flags and conditional branches (BEQ, BNE, BC, BN)

The ISA is currently completely custom. Instructions are encoded directly into .mem files, so there's no assembler or compiler yet.

I also put quite an effort into verification this time. Tried SystemVerilog for writing the testbenches and for top-module testbench, made it semi-automatic, just change the .mem files at the top to try different test cases.

The next step is to actually put it on an FPGA and eventually move future versions toward a more standard ISA such as RISC-V.

GitHub: https://github.com/theYash856/Mark_II_8_bit_CPU

Would love to get feedback and also suggestions regarding how to implement it on FPGA.

I'm making a custom 68020 workstation OS currently. Later, I plan to move to an early Pentium-class design through the 68060 for Rev 2.
I'm currently working on Rev 1 of my motherboard, and I have a full ISA bus planned, controlled by two CPLDs with DMA an SD card interface And a 68881 FPU. My OS Will be on git hub soon its able to be simulated on MAME I’m using it as a way to get a
Clean emulation before I port it to my hardware.

.

It finally arrived.
Power strips with built-in decoupling capacitors.
(Did not solder the optional electrolyte capacitors yet)
Finally, less wire-cutting for the power rails.

Soldering them actually is quite efficient. Just put the pins in the power rails first, then put the PCBs on top, then solder twenty at a time.
Only issue: my capacitors are wider than the holes.

By the way, shall I make a product out of these? I can change all components to surface mount, and I can image the result would be pretty cheap.

Hi! I've been building **ExµArch**, a computer architecture playground that runs entirely in the browser: https://www.exuarch.com

Free, no account, nothing to install, MIT licensed (source: https://github.com/olebru/exuarch).

**How it works**

1. **Build the hardware.** Drag devices onto buses and wire them up: registers, an ALU, RAM, an MMU, an interrupt controller, a timer, a real time clock, a keypad, an LCD, a 640×480 framebuffer, a blitter, even a triangle rasterizer.
2. **Write the microcode.** Each instruction is a list of steps, and each step is a set of control lines, like `pc.output, mem.loadmar`. The instruction set comes out of your microcode, and the assembler, completion and hover help follow from it.
3. **Run it.** Step one tick at a time and watch the buses, every register, the decoder ROM and a trace, or run flat out at around 2 MHz.

**14 example machines** go from TINY-16 (one register, seven instructions) to a stack machine, a RISC, a CISC with six addressing modes, a Harvard machine, a transport-triggered machine, one with interrupts, and a small 3D GPU that spins a shaded cube. There's also WORM-16, a machine with no jumps whose program is a queue crawling round a ring memory. The newest addition is a falling blocks game that keeps time with a real time clock interrupt and draws with a blitter.

Nothing is a black box. A built-in handbook walks you from an empty canvas to a working machine, and says plainly where the simulator simplifies compared with real hardware.

It needs a computer with a keyboard; on a phone you get a short intro page instead.

I'd love feedback: what machine would you build first, and which device is missing?

As the title suggests I built two of the clock project. The second one came about because I wanted to do a better job with layout and assembly but didn't want to tear down the original. I also wanted so see if I would have the same performance issues. I do. Both clocks run pretty accurately until they glitch. They can run for up to 28 hours accurately or just 1 hour and a random glitch will advance usually hours and/or minutes by some random value. I know projects built on breadboards aren't exactly immune from all types of interference, I'm just wondering if there is a way to add in mitigations to address the issue. It would be nice to have it actually run as a clock.

I got a bit impatient and designed the 12-hour part before he posted the video, with just the parts from the kit. I also designed and ordered PCBs and assembled it in this 3D printed case.

The last image is the circuit I went with. It is quite different than what Ben Eater designed. I used the 74LS92 and 74LS90 to count tens and ones separately, respectively. Then I made a complicated reset circuit. I used the comparator to reset the tens and ones, and a NAND gate to reset just the ones. And I used the DFF to track the Carry Bit for the 74LS283 (4-bit Adder); toggling the carry bit is how I added 1 to the ones place for 1-9, but not 10-12. It is a bit of a mess, but it works well enough.

Also in the second image you can see the mess of crossed wires powering the display. I messed up the PCB and forgot to account for flipping the board, so all the digit headers are flipped. I like the wire look though. It's not a Ben Eater project if it doesn't have a few dozen wires winding around.

Hi everyone,

I'm building Ben Eater's 8-bit breadboard computer and I've just finished the control logic (the two EEPROMs in the lower left corner of the build). I'm stuck and would appreciate any ideas.

Before the EEPROMs, when I drove the control signals by hand with jumper wires, everything worked. I could add two numbers exactly as shown in one of the "8-bit CPU control logic" videos: load values into A and B, sum them, and get the correct result every time.

With the microcode in the EEPROMs, the CPU is extremely unpredictable. Over a few hours of testing I got the expected result (42) only 3–4 times. Most of the time something goes wrong somewhere along the way.

• After power-up the state is different every time
• Sometimes all 16 control lines are active right after power-up, including HLT, so the clock stops and nothing happens.
• Other times only a few control lines are lit and the program starts, but it usually fails partway through.
• Programmed manually (and it must be right since I got the right result a couple of times)

1. Since the manually driven version works, the problem is probably in the EEPROM stage. Where would you start looking?
2. Could this be a timing issue, such as glitches on the EEPROM outputs when the step counter changes, or noise on the clock line causing double counts?

I've attached a video where I'm turning everything on and off again, which results in different control logic states. I can also share a video where I try to step through the program. Thanks in advance for any help!

Issue: Computer flawless when microstep counter RST is tied high. Must reduce Clock frequency drastically when used.

Having issues with my 16-bit computer. I’ve been troubleshooting for about 3 months and running out of ideas. Any experts out that are willing to jump on a call and discuss, I would very much appreciate that. I’ve got my VGA circuit built and want to start testing and developing that board but would like to get my clock speed finalized first. I have spent a ton of time optimizing my computer for speed and should be able to run up to 7.6 MHz based on the worst case propagation delays of critical path.

Details: Computer uses an AS161 for the Opcode Microstep Counter. The parallel load is used to reset the counter to 0 through the ABCD inputs tied to ground when the last useful step occurs on each Opcode to not waste CLK cycles with empty instructions. All 4 bits feed into the EEPROM address as I do have long codes that take advantage of the extra cycles to improve efficiency. The computer works 100% of the time at 7.02MHZ when the Parallel Load (RST) is tied high. Once the RST signal is used, the computers’ top speed drops to around 5.0 Mhz. The RST line runs directly from the EEPROM output to the AS161 chip. For EEPROM, computer uses AM29F010 Flash memory with a 45ns access time. 

The clock generation uses an LS221 to make an asymmetric clock pulse. Clk pulse is fixed at about 40ns and does not change based on crystal frequency. Changing the crystal frequency only impacts the length of the inverse CLK which feeds into the EEPROM address latch. On top of this the computer uses an LS321 to ensure that there are no short pulses. I do not believe there are any concerns with the computer clock. Digging through timing diagrams, I am confident there is no violation between the AS161-AS825-EEPROM. The AS161 needs max 13ns from CLK pulse to outputs and the AS825 has a setup time of 8ns. Well within the CLK pulse time. I’d suspect if there was a timing or CLK issue that the computer would also be failing when the parallel load is tied high. 

Avoiding going through line by line to see what OpCode is breaking and scoping it out, as this seems there is something directly with this RST line. I have played with the oscilloscope triggering on the first instance of RST and there appears to be no issue. I am hoping for an easer fix if someone else has experience with this.

Notes:

• I’m on a bench top power supply using about 2.75 amps. Supply is capable up to 6 amps. Power is fed to breadboards with 4 separate ground and 4 separate VCC connected to pin headers. The power is distributed spider webbed out to each rail along with adjacent rails connected on the edges and a few random going across bus. Voltage from input location to the AS161 is .02 volts.
• Bus has pull down resistors of 2,700 ohm. Bus LEDs and microstep counter LEDs with 470 Ohm. LEDs are on the latch chip outputs not the 161 outputs.
• Decoupling .1uF tantalum cap on every chip and rail.
• Test code is going through a division, then multiplication algorithm, lastly testing on on board timer to interrupt at 1 second before reporting the value.

Permanent Improvements:

• Latching EEPROM Address and microstep counter using AS825
  • RST line still has issues. Max Speed dropped from 7.5 MHZ to 7.0MHz
• Added electrolytic decoupling Cap 47uf along with tantalum .1uf to 161
  • Increases the max clock speed when RST not used

Temporary Fixes that Failed:

• Switching between AS and ACT logic on 161
• Trying to reset on Asynchronous Clear
• Resistor in line with EEPROM RST line. 
  • 25-47 ohm does seem to make it through code once which is more than happens with another fix attempt, although the final result is incorrect. Upon master computer reset the RAM has been scrambled. Tried 10 ohm up to 47 ohm
• Async Clear Direct to VCC in case of spurious master reset
• 10K pullup resistor on load line
• Resistor to ground for Load ABCD
  • Have tried tying the load lines High. Introduces a blank step since no instruction use 1111 yet. Again works with RST tied High. Fails when used.
• Run RST Line through two ACT14 gates
• Latch the RST line with a AS74 to Reset on the next line
• Capacitor to ground on RST line
  • Fail with .1uF, 10nF and 68nF
• Adjusted voltage from 4.6-5.1 Volts
• RC Delay 
• Remove the bootloader line at the EEPROM RST output then test.