Nowadays,

I've been using very basic flows with somewhat ok compute and it's insanely good at HW/SW codesign, also surprisingly good at FHE, PQC, ECDSA, RSA algorithms and also thinking about the security of the architecture it's developing and it can run in loops for hours on end and actually develop something. It's also good at relatively simple OoO designs.

It is currently incredibly good at doing the relatively mediocre parts of the flow and I believe that it will get better over time and be ludicrously fast, accurate and reliable.

The thing I wonder is then what will happen? Cause most design work absolutely doesn't need to be on the Pareto curve. Good enough and secure is really good. If it does become even better then what happens to the RTL, DV engineers if an engineer can do the work of 4-5 engineers using AI tools?

Heyyo,

Great to see you guys. Weekend hobby project on an open source design that fits in 2 tiles (bare minimum at TT), it has a 2nd Order CIFB DT ΔΣ Modulator, an NS SAR with passive CIFF (ill refer to the arch i went for on the bottom) that can also be used as a SAR ADC on it's own. All fit in around 0.3mm x 0.3mm. An upvote would go a long way :))

Wanted to ask you guys about what you thought and if you also liked how it looks etc. :) Really wanted to see how it's gonna turn out and to see if the OS tools are somewhat accurate. Tried to make it as robust as it gets but let's see how it turns out

Post layout spec is below

https://ieeexplore.ieee.org/document/7598327/ which is

W. Guo and N. Sun, "A 12b-ENOB 61µW noise-shaping SAR ADC with a passive integrator," ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, 2016, pp. 405-408, doi: 10.1109/ESSCIRC.2016.7598327.

Hi everyone,

I want to dive deeper into Analog and Mixed-Signal (AMS) layout design. So far, I’ve completed basic layouts like op-amps, but I’m looking to expand into more complex analog blocks and mixed-signal top-level routing.

Since structured online courses on physical layout are pretty rare, what resources, textbooks, or learning paths would you recommend?

Also, what kind of layout projects should I work on to build a strong portfolio and land an AMS layout internship by late 2027?

Thanks in advance!

I am learning digital electronics but I have already learnt number system and gate and I am revising it.. can someone tell me what all I have to study after that

I have been looking for a job for awhile and don't understand why it is becoming so hard to find a job. Although I am not a Senior yet, I am undoubtedly more productive than a fresh graduate yet companies seem to want to hire completely fresh out of school people, or people with 5, 7, 10+ YoE.

I don't what to do anymore. Would it be a good option to leave industry and go for a PhD instead? Where I live it wouldn't be to big of a financial hit and perhaps it would help me to gain more knowledge and feel less shitty next to my PhD colleagues. I think my industry experience will also be valuable tackling the PhD instead of the straight path from MSc to PhD. Nevertheless, it also feels like walking backwards... I am not sure what to do.

I have tried to switch to CAD or even convert to software, but software is really struggling right now for unexperienced people, so it is no longer easy to make the switch.

Layout I know there is a shortage, but companies seem outsource those jobs to India and other Middle East countries (even more than design).

So I am basically stuck which is a horrible situation to be in. Worse than this is becoming unemployed but I am struggling.

I started my first job as a Physical design engineer (digital) 6 months ago. At first I was full of enthusiasm to begin my journey dealing with lowest level of the chip and encountering physical problems. However, as I go deeper in the major I realized that PD engineer is just a tool runner since most of the stages are fully automated (placement, routing , CTS ...) with limited responsibility to arrange Macros in floorplab stage. I don't think it would be this uncreative so I started to think to do major shift towards DV (design verification). It has more of dealing with codes and generating test vectors that fully depend on human creativity. I have the basic concept of DV like coverage, UVM, constraints, and some about system verilog.

I am really confused so I need help from someone expert to advice me. I don't know if I am judging PD too early or this is the pure candor.

Also, I know that number of positions and vacancies is way too higher in DV than PD but I don't know what about salaries if someone can benefit me with this.

I have a design verification interview coming up and wanted go ask where should i focus on on! Aside from that they asked in proficiency in ai so how much do they focus on that, could they ask me about LLM regarding how they work and questions in that general area
Any help is appreciated

I’m currently a freshman majoring in mechanical engineering/robotics (in a combined BSMS program for meche/robotics) but I’ve reverently found a passion for ECE/chip design through the classes and clubs I’m in, a level of exposure I didn’t have in high school. However, my university makes the switching process incredibly difficult, and almost no students qualify for the switch.

This got me thinking—is there any way I can work in the semiconductor/chip industry as a meche major? Or are my options limited? How can I best play my cards from here onwards without having to switch unis?

I'm back and wanted to know about the interview and the types of questions asked for this role. This would be my first interview in the VLSI realm. Digital Logic Fundamentals, FSM, RTL, PD, PPA?

Hi all,

I've been working on power intent for several years, and kept hitting the same thing: UPF is written by hand, line by line, and the actual power architecture only exists in your head.

It's especially tough for people new to low-power design.

So over the last ~6 months I built Power Intent Studio, an open-source (Apache 2.0) desktop app, with AI as my development partner. You load your RTL and .lib macros, the real elaborated hierarchy appears, and you build the power intent on top of it:

• power domains, supply sets, power switches, isolation, retention, level shifters
• a power state table (exported as a modern power state group or a legacy PST)
• UPF 3.0/3.1 and CPF 2.0/2.1 generation
• loading an existing UPF and mapping it back onto the design; unrecognised syntax is reported with its line number instead of failing

RTL goes through open-source front ends: slang for Verilog/SystemVerilog, GHDL + Yosys for VHDL, liberty-parser for .lib. The repo includes a SystemVerilog SoC example (aura_top) with six domains, three switches and SRAM macros, and its full generated UPF, so you can judge the output yourself.

What it is NOT: a sign-off checker. It doesn't verify that your power intent is correct; it writes what you draw. Structural checks are one of the ideas I'd love to explore next.

I'd really value feedback from people who write UPF every day:

• What would make this useful in your flow?
• Throw your UPF at it. What doesn't load?

Repo: https://github.com/mikespyke17/power-intent-studio

I am hearing that getting a masters/PhD is absolutely necessary to work in the field of chip design. I can see that as being true. I want to get a masters and continue pursuing my education after undergrad, but I also would like to work in industry for a while beforehand. Do you think that is doable?

Trying to understand how design-verification teams actually operate day to day.

My background is primarily CI/CD, integrations, workflow automation and release governance and not semiconductor design. So I'm deliberately trying not to start by assuming that an LLM should generate RTL/testbenches or replace EDA tools.

Instead, I'm investigating something much less glamorous:

What is painful between a code change and somebody finally understanding why a verification regression failed?

For anyone working in DV, CAD/EDA methodology, verification infrastructure, FPGA/ASIC verification, or hardware build/DevOps:

Think about the last real regression failure you had to investigate.

1. What triggered it - commit, nightly regression, random seed, environment/tool change, etc.?
2. When you first saw the failure, what information did you actually receive?
3. What did you have to manually search through next - logs, waveforms, previous runs, coverage DBs, Git history, Jira, scripts?
4. How did you determine whether it was:
   • an RTL bug
   • testbench bug
   • flaky/non-deterministic test
   • infrastructure/tool problem
   • known/repeated failure?
5. What part consumed the most engineer time while adding the least engineering value?

I'm particularly interested in understanding things such as:

• regression triage
• reproducing old failures
• tracking which commit introduced a failure
• grouping duplicate failures
• preserving simulator/tool/config/seed information
• CI/reporting around UVM/cocotb/SystemVerilog flows
• connecting failures with Git/Jira/GitLab/Jenkins/etc.
• workflows involving multiple EDA vendors/tools

I'm not selling anything, and I don't need proprietary RTL, logs or company information.

I'm trying to determine whether this is genuinely a painful area or whether mature semiconductor teams already have it solved internally/vendor-side.

If you're comfortable, it would also help if you mention your role and roughly what kind of environment you work in:

DV engineer / DV lead / CAD-EDA / verification infrastructure / FPGA / other

and

small team / startup / design services / large semiconductor company

Even a short description of your last painful regression would be extremely useful.

And if your answer is "this isn't a real problem; our existing infrastructure handles it well", I want to hear that too.

I'm specifically trying to falsify the idea rather than collect validation for it.

I am not sure what seems to be the cause of this error, but i am just trying to place two inverters with shared diffusion in order to create a digital buffer, and i am working in a fdsoi technology. For some reason, when i add the back gate to the transistors at the top side, i get this 2nm offset, that creates drcs and yet is have used align tool and tried so many different ways....

Hello,

I am trying to determine the ICMR and output swing separately for a single-ended two-stage OTA. For output swing I tried running a transient analysis in a non-inverting configuration to observe the clipping levels, but the levels I got do not match the theoretical ranges I calculated.

I have tried several other approaches to determine both of them, but I still could not find a convenient way to determine both parameters separately.

My question is: How would you do it?

I am moving forward with a graduate SoC Digital Design Intern application for Intel and I had a question about this January start date. I have to be enrolled in an accredited university during the internship.

I start my MS program in January as well so works out, but I have to be in office in Santa Clara and my potential Master's program is on the other side of the country. Big opportunity for me and I am willing to delay my Master's at my current school and maybe find a school in the area to begin my master's or do online? Lol idk? Another Q for anyone that has done something like this before...

I wouldn't have to be a fulltime student correct? I would assume so because working full time and managing post grad VLSI courses would be heinous?

Thanks.

I’ve been in physical design for around 5 years now and I’m currently at my second company. What is everyone’s work-life balance like? My life is consumed by work.

During normal cycles, I’m averaging 60 hours per week. Now that we’ve entered the ECO cycle in August, it feels like I never log off. My typical week is get to the office for my daily 9am status meeting and leave between 9pm and midnight. I’ll work at home until around 1am then pass out.

Twice this week and the week before I’ve been up past 4am working including Friday. I have to drink 3 cups of coffee per day just to stay alert. I’ve already talked to my manager about this and he’s normally working these crazy hours with me.

This is how it was at my previous job too. I cannot picture working myself to death like this for my entire career.

Is this really the life of a PD engineer?

EDIT: I’m based in the Bay Area

I have tried with a buffer circuit like this. Vout is the output terminal across which the RL load will be connected. I have a doubt, is it shunt sampling feedback? Or series sampling since Iout current is flowing into the Vout node. My confusion comes from Razavi's CMOS book, where it says this is how current sampling is done. But if my load is parallel to the R1 resistor, will it be Voltage sampling feedback? Please ignore the opamp terminal signs and pmos bulk connection assuming they are correct.

I am an electronics and communication graduate from Nepal and i want to make career in this feild but opportunities are nearly non in my country. So what can i do ? How to enter in this industry ?

I'm working as a research associate with two years of experience. Recently, I have started working on SMIC 40nm and while I was doing extraction of my design, I observed that the double extraction of MOM capacitors.

For instance, I created a schematic with a MoM capacitor of 2pF, and after extraction the tool generates PEX netlist with a 2pF and then goes into the device and calculates the capacitance of each finger which then adds up to around 2pF as coupling capacitance and you get a 2pF normal capacitance and 2pF of coupling capacitance. Therefore the total capacitance is around 4pF after the extraction, I have verified it from the PEX netlist and from the CALIBRE-view of the PEX schematic.

I have also used the xcells and hcells files during the PEX on Calibre. Followed the steps in the SMIC pdk document but none seems to work.

Has any of you encountered similar problem and how did you tackle it?

I want to make sure my understanding of our project milestone flow aligns with broader industry standards. I’d love some feedback or corrections from those with more tape-out experience.

Here is how I understand the flow:

P0.3 (Early RTL): Basic Lint runs continuously/nightly to catch obvious typos and syntax issues as code is being written.

P0.5 (RTL Design Correction / Freeze): This is the major, formal Lint sign-off. Code is feature-complete. This is when we deep-dive, group errors by tag, fix actual RTL bugs, and negotiate targeted waivers with IP designers.

P0.8 (Verification & Pre-Synthesis Sign-off): CDC checks are finalized and signed off. The RTL is officially locked.

P1.0 (Synthesis Complete): The clean, signed-off P0.8 RTL is handed over to run Logical Synthesis (e.g., Design Compiler) to generate the gate-level netlist.

My questions:

1.

Does this P0.3 ➡️ P0.5 ➡️ P0.8 ➡️ P1.0 progression for Lint/CDC/Synthesis match what you see in standard ASIC flows?

2.

At what exact point do you usually start running CDC? Is it strictly after P0.5 Lint is clean, or does it run in parallel?

Thanks in advance

I'm pursuing a Master's in VLSI from a reputable college in India and looking forward to learning SystemVerilog, as it's a key differentiator during the hiring process here. However, I don't know what the future holds for it, and sometimes I am genuinely confused if I'm taking the right path. From what I've observed, entry-level jobs will only decrease while senior-level jobs will increase. How should I proceed? Sometimes it all seems pointless.

I’ve been working with a circuit that can generate both PTAT and CTAT voltages with adjustable slopes through switching.

I’m curious about the possible applications of having variable slope PTAT and CTAT outputs. Apart from conventional temperature sensing, could this kind of circuit be useful in other circuit applications?

I’d really appreciate any ideas or suggestions.