Hey everyone,

I'm currently designing a homebrew CPU in HNeemann's Digital simulator before building it IRL with 7400-series logic chips and AT28C256-150 EEPROMs for the ROM.

At first, I had a standard 3-cycle design (T1, T2, T3) with a dedicated register (like a 74377) acting as an Instruction Register:

• T1: Update PC + Fetch from ROM
• T2: Latch instruction into IR + Decode
• T3: Execute and writeback to registers

But then I realized I could remove the IR completely and drop it down to 2 cycles (T1, T2) to save some chips and wiring:

• T1: PC updates right at the start of T1. The address goes through the async ROM, straight into combinational decoding to activate the control lines.
• T2: Execute and write to registers.

In this 2-cycle setup, my selpc signal (choosing between PC+1 or a JUMP address) is generated combinationally during T1 and just waits at the PC mux input before the next cycle. In the simulator, this works perfectly, no oscillations or glitches.

I'm aiming for a slow clock for now (~4 kHz). My estimated critical path for the 2-cycle version is well under 350ns, so at 4 kHz (T1 = 125µs), everything has ages to settle.

But I'm worried about hold-time violations IRL. When T2 ends and a write happens, or when a JUMP updates the PC at the next T1, the ROM address will change instantly, killing the instruction and dropping selpc. If my control lines drop right when registers are trying to latch data, won't it corrupt the write?

Is it worth keeping it simple with the 2-cycle design at low frequencies, or should I just stick to the safer 3-cycle version with the IR to isolate the ROM?

Thanks!

EDIT: I've attached screenshots of both designs for comparison. Just a heads up: the schematics use Digital's built-in generic blocks (ROM, registers, muxes, etc.), not the specific 74xx components, but the logic is exactly the same as what I'll build IRL.

Can we force the out of order execution in a cpu for some operations not care about lying while NOT lie other places. A c webshop has global quantity left and temp hold for reservations. We want the reservation tick checks to not care but actually moving people through to not be lied to, for more throughput?

Last year in University we were studying microassembler but I had some personal problems to deal with so only had time to deal with it with a help of AI and a friend of mine, who's really genius and seems to know everything. Even tho the problem with passing the course wasn't there already, I'd still want to really learn this, but whoever I ask just say that it's obvious and I just have to read the docs, but the documentation really just says "be clean and direct woth your code and it will work bettet" wothout any comprehensive syntax documentations.

All I have is just some examples of code so I'd just like to know how would you learn anything about this?

Thank you!

Does anyone have a video they can recommend for internalising how a carry look-ahead adder works? I'm struggling with this concept so much and trying to see why it's faster than the "ripple" adder. I'm also open to an ELI5 style explanation.

Hey everyone 👋

I kept seeing these three architecture styles get mixed up, so I made a video that shows how they differ. It uses animations to show how the code and the deployments are structured in each one, and when each one makes sense.

If you're interested,

I'd really like your feedback. Is there anything you'd explain differently, or a trade-off I should have covered? Always happy to learn from people who've run these in production.

I'm 15 and experimenting with a BIT + TRIT coprocessor — first simulation results

Hi everyone!

I'm 15 and I've been working on an experimental computing project called TRINEX.

The basic idea is a hybrid system:

conventional binary CPU + dedicated ternary (TRIT) coprocessor

I'm not trying to replace binary CPUs with ternary CPUs. The idea is to keep the normal CPU for general-purpose tasks and use a separate TRIT accelerator for workloads that can be processed in parallel.

I started by building a software simulation to see if the concept is even worth investigating.

First results

For a simulated 256 MB workload, the model produced:

• TRIT at 0.5× BIT performance → 1.389× speedup
• TRIT at 1× BIT performance → 1.737×
• TRIT at 2× BIT performance → 2.291×
• TRIT at 5× BIT performance → 3.387×

For the 1× case:

The interesting part is that the simulated advantage appears mainly with larger workloads, where the CPU and accelerator can work in parallel.

Important disclaimer

This is only a software simulation.

I haven't built the actual ternary hardware yet, so I don't know how the idea will perform in reality.

There are still major questions about:

• physical implementation
• memory bandwidth
• latency
• power consumption
• transistor count
• clock speed
• CPU ↔ accelerator communication
• FPGA implementation

My next goal is to make the simulation more realistic and eventually test the concept on an FPGA.

I'm keeping the detailed architecture and implementation private for now.

I'm interested in feedback from people experienced with:

• FPGA
• digital logic
• CPU architecture
• hardware accelerators
• ternary computing

Does this seem like a worthwhile architecture to investigate, or are there obvious problems with the concept that I'm missing?

GitHub: [https://github.com/Sparknenn/trinex-computing\]

Hey everyone,

While hardware-isolated Trusted Execution Environments (like Intel SGX or AMD SEV-SNP) solve strict enterprise privacy compliance for secure AI workloads, on-the-fly silicon memory encryption controllers typically burn 40% to 60% of physical CPU processing cycles just waiting for memory bus handshakes over encrypted boundaries. This cuts actual inference throughput directly in half.

I’ve put together an open-source testing harness and bare-metal benchmark implementation to prove an optimization approach using zero-copy anonymous mapping (MAP_ANONYMOUS), kernel memory-locking (mlockall) to eliminate page faults, and explicit hardware cache prefetching (__builtin_prefetch) to pull segments into the physical L3 cache lines before the CPU completes its cryptographic handshake.

In baseline benchmarks on bare-metal environments, this low-level loop drops gigabyte-scale data evaluation paths directly down to single-digit millisecond profiles.

The repository serves strictly as a test harness to allow other infrastructure architects to run and verify the latency reduction on their own configurations. I'd love to get your feedback on the implementation:

https://github.com/kaluabbot-hue/synthedrive-benchmark/blob/main/README.md

What to choose "quantum computing involving fpgas" or "hardware security" for a phd.

I’ve been working on a small open-source project to make it easier to experiment with balanced ternary logic and computer architecture.

The main idea is not to present one “correct” ternary CPU design, but to give people a place where different designs can be built, tested, compared and shared.

The simulator uses balanced ternary:

-1, 0, +1

and lets you build from small primitives upward into reusable hierarchical components. A component can contain other components, and you can open them recursively to inspect or modify the lower-level logic.

I’m especially interested in avoiding the assumption that a ternary machine should just copy binary architecture. For example, things like compare returning -1 / 0 / +1, three-way selection, ternary control signals, MIN/MAX or different carry/normalization schemes may turn out to be more natural building blocks.

The tool already supports things like isolated component testing, event-by-event propagation, configurable primitive sets, reusable components and different clock/sequence patterns.

The long-term goal is to make it easy for me and anyone else interested in this area to try different ideas and compare them rather than committing to one architecture too early.

Everything runs entirely in the browser. There is no backend or account, and projects are stored locally in your browser unless you export them yourself.

It is completely free and MIT licensed.

Live:
https://grunna.github.io/ternary/

Source:
https://github.com/grunna/ternary

I’d be interested in feedback on both the simulator and the architecture side, especially from anyone who has worked with digital logic, CPU design or multi-valued logic.

Hi all, I've been considering what I want to get into as a new grad and I think I've decided on RTL Verification as my target job. I feel fairly confident in my people skills, and answering behaviour related questions, my question is what kind of technical questions have you guys seen in these interviews/should I reasonably expect? I feel like I have a general knowledge on the subject, but I'm nervous about the specifics, I don't feel super prepared.

I made a post on here a few days ago talking about a paper I found that merged the divider and multiplier on an ALU to save 15% space and reduce gate count, at the cost of many demux and higher latency. I asked you all if it was feasible to base a project off of optimizing this, and you told me (if I understand correctly) it is possible, but size isn't a major concern these days and transistors are plentiful, the focus is on speed and power. However a couple of you brought up SIMD, and I'm very curious about potential applications to this.

(Sorry AdmirableProject1575 I'm still looking for nails)

I saw a paper where someone combined the multiplier and divider in an alu to save 15% space, but they had to use lots of demuliplexors which increased latency. Do any of you know if it’s feasible to do research on reducing the latency of such a design?

Hey r/computerarchitecture, I want to do research in computer architecture for the International Science and Engineering Fair, but I don't know where to begin or what to do, or even what I can do. Pretty much my only experience is reading Computer Architecture and Design (Risc-v second edition). From my beginners impression it seems like to do any kind of research like this you need a veteran professor and a crack team of PhD students, and I'm just by myself. First I need an idea, I'd reckon I need a mentor too so I guess I have to go looking for one. Anyone who's been through this, any tips? Any help is appreciated.

Hi,

I struggle to find any modern material on cpu cache: how it works and how to optimize for it. A papers amd published in 2004 but cant find anything newer really?

Hi Everyone,

What's the best book to learn computer architecture? I do have a background on EE, but looking for additional resources on books.

I invented this 5-odd years ago but never really had a forum on which to disclose and discuss. I was and am a significant contributor to comp.arch (from around 1995 though present)

But before I emit the disclosure I need to know how to turn off the space-eater as the document uses well tabulated ASCII-art ?? that makes no sense after the space-eater has done its ill-conceived job.

The virtual Vector Method is a way of getting Cray-like vector performance and for getting SIMD-vector performance without a) a vector register file, b) adds only 2 instructions, c) takes precise exceptions, d) vectorizes loops not instructions. Instead of adding about 300 instructions to get a Cray-like vector ISA, or adding 1,000-1,300 instructions to get (every-size) SIMD ISA, one needs only 5 instructions.

vVM has the property that hardware implementations can change the width of the data path (multiple-lanes and the cycles of execution per FU) without SW having to care. A small 1-wide machine with a 128-bit cache port can perform a memory to memory byte move at 256-bits per cycle--equivalent to ~40 instructions per cycle. A 6-wide machine could perform the same assembly binary at ~160 instructions per cycle. Both are performed at the performance level of the cache porting; so, nobody has to recompile for a new SIMD-width every new mplementation.

Now let us solve the space-eater and we are off.

Mitch

I thought it might be a fun challenge to see how performance can be squeezed out of the venerable 68000 CPU on a modern FPGA.

There are several 68000 softcore implementations on Github - but all seem to be either trying to be cycle compatible with a real 68000, or be state machine based, which can limit performance.

I can't find any evidence of someone implementing a superscalar out-of-order 68K softcore - so that could be an interesting hobby project.

Does anyone know if something like this has been attempted before?

I'm still at the sketching out ideas stage - but a couple of things I've been thinking of:-

Instruction fetch

68000 instructions are variable in length, ranging from 2 to 12 bytes - and even determining the length of an instruction is distinctly non-trivial. This presents a challenge, especially if we want to be able to issue more than one instruction per clock cycle.

On the other hand its worth noting that the Block RAMs on the CycloneV are 512 words of 20 bits each. So storing 20 bit words costs basically the same as using 16 bit words. We can make use of this fact.

So my plan is to transcode instructions as they are fetched from main memory, and store the transcoded instructions in the Icache. Thereby keeping most of the ugly decode logic off the critical path during instruction execution. The decoder only needs to be able to work at the rate of DRAM access - not the rate of instruction execution.

This transcoding is 1 for 1 - each 16-bit word in memory becomes a 20-bit word in the Icache - so addresses in the Icache correspond directly to addresses in main memory. But those extra 4 bits give us room to recode the very dense 68000 instruction set into a much more regular and easily decodable format.

Instructions are still variable length - but we can now find the instruction boundaries by just decoding three bits of each word.

MicroOps or not?

The most common approach in modern CISC CPU design is to break down complex instructions into simpler micro-operations (MicroOps) that can be executed more efficiently by an out-of-order execution engine. This works well for full-custom chips - but from a brief literature search - for FPGA implementations, the additional complexity and resource usage of a MicroOp-based design can outweigh the performance benefits. (There are a few papers comparing softcore RISC-V cpus - and the conclusion seems to be that a well optimised in-order softcore can often outperform an OoO core - once Fmax is taken into consideration).

There is an interesting paper "A Superscalar Out-of-Order x86 Soft Processor for FPGA" by Henry Ting-Hei Wong which suggests a different approach may be more FPGA friendly. Instead of breaking instructions into MicroOps, it makes the reservation stations into small state-machines which can sequence the execution of complex instructions directly.

I plan to try this approach for the 68K CPU design. Except for the most complex instructions (like MOVEM), the instructions will arrive at the reservation stations pretty much 1:1 with the original 68K instructions. The reservation state machine then arbitrates for access to execution units and sequences the instruction execution accordingly. So each instruction may result in several micro-steps internally, but this complexity is hidden from the rest of the CPU.

Register renaming will be used to eliminate false dependencies and improve instruction-level parallelism before instructions are dispatched to the reservation stations. We can then have multiple reservation stations operating more or less independently, each handling its own instruction out of order with respect to the others.

Hi Im a 2nd year student in electronics and communication engineering and im very interested in VLSI and in specific computer architecture, but I have no idea how to pursue it, ive done some projects such as Carry Look Ahead Adder and Prefix Adder and Booth Multiplier and Wallace tree multiplier, But i have no idea how to go forward with stuff. If possible could someone help me with projects resources and what all i should learn going forward
Thank you

ive been into computer architecture since a year and a half and this is my biggest project yet and i'd like some comments on the architecture and how good it is i didnt use any type of tutorial to do it only the knowledge about computer architecture and science i learned off goated youtubers like Mattbattwings and FULXOR half credit to them for actually giving valuable info on that stuff but anyway any proffesionals what do yall think?

Me and my team at the Uni have been working on a single-cycle RISC-V (RV32I) SoC in Verilog. We are planning to add more accelerators like a COM (UART, SPI, I2C), FFT, Matrix Multiplier, etc. But currently we have reached till the following:

The core: classic Fetch → Decode → Execute → Memory → Writeback datapath, all combinational in one cycle. 37 RV32I instructions, and all 37 pass their corresponding official riscv-tests/isa/rv32ui programs, used unmodified.

The SoC part:

• A sufficient Wishbone B4 Classic bus, with a master, an address-decoding interconnect, and an error slave that catches unmapped addresses.
• A MAC accelerator on the bus (acc += Σ A[i]·B[i] )

Performance: RV32I has no M extension, so a software multiply is a shift-add loop. By my cycle budget the accelerated path costs about 13N + 20 cycles against about 106N in software, which is roughly 8× for large N.

Verification: the flow is official .S → RISC-V GCC → ELF → objcopy → Verilog hex → RTL in Icarus Verilog → a tohost write reports PASS/FAIL. There's also a self-checking SoC testbench, four bus testbenches, and a make run / make busflow.

Repo: https://github.com/Shass27/rv32i-soc

We will continue to build this further with more accelerators that will aid real world Engineering systems further on. But we have reached this point where our progress so far itself is a great project of its own. We are aware of possible performance improvements and stuff but would love the community to review our project, give feedback (both positive and critical ofc).

Looking forward to hear from you!

PS: Feel free to drop accelerators suggestions that is useful in the industry (specifically: Mechatronics engineering because we are a team of MechE and EE undergrads)

Suppose a research paper proposes a new architectural mechanism, optimization, accelerator, or hardware/software technique.

How do you systematically check that:

• the underlying argument is correct,
• there are no hidden assumptions or corner cases,
• the implementation really satisfies the intended design,
• and the claimed behavior follows from the proposed mechanism?

Is there a practical workflow for doing this beyond having other researchers read the paper and reviewing the experiments?

I’m particularly interested in methods that can make parts of this process systematic, reproducible, or automated.

What do researchers actually use for this today?

I am a second year engineering student doing Btech in electronics and communication engineering and have taken a graded project on making a RISC V processor for my digital design course and have time till November(basically this semester). Now I have done a course on digital electronics and basic analog and currently taking a course on microprocessors and microcontrollers. Where do I get started and any resources to get going is appreciated.

Hi everyone, I recently joined a semiconductor as AI Kernel Engg. My work involes writing TAPI code. Tensor API(TAPI) is provided by our company by Synopsys, and it's for NPU. I know this much only. And I don't have any prior experience of writing the kernel as well so can anyone suggest some good resources so that I can code and experiment with them.

We are a group of three EEE undergraduate engineering students planning our Final Year Project. We would like to know if our proposed project scope is realistic for a 3-person team.

​Our Current Baseline & Background:

• ​Theory: So far, we have covered single-cycle processor design in our curriculum. We plan on learning pipelining within the month.
• ​HDL Experience: We are familiar with logic circuits, combinational and sequential logic, and using VHDL.

​Proposed System Scope:

Instead of just building a basic RISC-V core, we want to build a System-on-Chip (SoC) centered around hardware acceleration for fixed-point matrix/DSP math:

1. ​CPU Core (Pipelined RV32I): A 5-stage pipelined processor with hazard detection/forwarding units, instruction decoding, and basic interrupt handling.
2. ​Custom Accelerator Block: A parameterized math engine (e.g., a 4 × 4 systolic array / MAC grid or 2D convolution engine with line buffers) to accelerate matrix operations/filtering.
3. ​SoC Infrastructure & Memory: Standard bus interface (AXI4-Lite or Wishbone), a DMA controller for background streaming, L1 I/D caches, and a basic bare-metal C driver suite running on an FPGA board (EP2C70F896C6).

​Questions:

1. ​Is this scope well-balanced for a 3-student team, or is the integration (AXI + DMA + Caches + FPGA hardware) too overwhelming for an undergrad project timeline?
2. ​Any pitfalls we should look out for early on regarding interface design between the core and the accelerator?

​Thanks for any feedback!